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RTL Design Engineer Location: US-CA-Santa Clara Jobcode: 905c48cc6b216ed1267cd7135a757b16-122020 Email Job
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Minimum Qualification :
- Minimum 5+ years of experience.
- Strong fundamentals in digital ASIC design; experience using Verilog or VHDL
- Experience with ASIC design/micro-architecture, synthesis, timing/power analysis
Preferred Qualification:
- Knowledge of SOC architecture
- Familiarity with high performance and low power design techniques
- Some hands-on experience in DV or PD.
- Knowledge of FPGA, emulation platforms & assertion-based formal verification
- Knowledge or experience in any of the following, fabric, memory controller, security, caches, coherence, MMU, high speed interfaces/protocols.
Mobiveil Technologies Inc.
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