We are currently on a hunt for a Hardware Verification Engineer to join our client's team in Santa Clara, CA.



What you’ll be doing:

• Responsible for all aspects of verification methodology employed and for ensuring the application of uniform standards and adoption of best practices.


• Work and liaison with other Design Verification teams within our customer sites to identify holes in the design verification flow and implement corrective action.


• Implement test benches, run regressions at RTL and gate level, run CDC verification at module and top level, generate and report DV metrics 


• Responsible for oversight and completion of debugging problems and troubleshooting in Real Time.


• Responsible for Debugging Designs for High throughput, Low Latency of Pipeline and Dynamic Power Management at full system level.

We would love to hear from you if :

• You have 8+ years of experience in System Verilog & UVM.


• You have BS/MS Degree in Computer Science/Electrical Engineering


• Advanced knowledge of ASIC design and verification flow.


• Sound knowledge of ARMv8, interconnect, memory coherence and memory architectures.


• Team player with excellent communication skills and the desire to take on diverse challenges.

PS:Excellent Base Pay + Benefits + Relocation.

We embrace diversity and equal opportunity in a serious way.